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rev. b a ad8065/AD8066 * high performance, 145 mhz fast fet op amps information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. * protected by u.s. patent no. 6,262,633 features fet input amplifier 1 pa input bias current low cost high speed 145 mhz, ? db bandwidth (g = +1) 180 v/ s slew rate (g = +2) low noise 7 nv/ hz (f = 10 khz) 0.6 fa/ hz ( f = 10 khz ) wide supply voltage range 5 v to 24 v single-supply and rail-to-rail output low offset voltage 1.5 mv max high common-mode rejection ratio ?00 db excellent distortion specifications sfdr ?8 db @ 1 mhz low power 6.4 ma/amplifier typical supply current no phase reversal small packaging soic-8, sot-23-5, and msop applications instrumentation photodiode preamp filters a/d driver level shifting buffering connection diagrams general description the ad8065/AD8066 fast fet amplifiers are voltage feed- b ack amplifiers with fet inputs offering very high performance and ease of use. the ad8065 is a single amplifier and the AD8066 is a dual amplifier. the fast fet amplifiers in adi? propri- etary xfcb process allow exceptionally low noise operation (7.0 nv/ hz and 0.6 fa/ hz) as well as very high input impedance. with a wide supply voltage range from 5 v to 24 v, the ability to operate on single supplies, and a bandwidth of 145 mhz, the ad8065/AD8066 are designed to work in a variety of applications. for added versatility, the amplifiers also contain rail-to-rail outputs. despite being low cost, the amplifiers provide excellent overall performance. the differential gain and phase errors of 0.02% and 0.02 , respectively, along with 0.1 db flatness out to 7 mhz, make these amplifiers ideal for video applications. additionally, they offer a high slew rate of 180 v/ m s, excellent distortion (sfdr ?8 db @ 1 mhz), extremely high common-mode rejection of ?00 db, and a low input offset voltage of 1.5 mv max under warmed up conditions. the ad8065/AD8066 operate using only a 6.4 ma/amplifier typical supply current, while they are capable of delivering up to 30 ma of load current. the ad8065/AD8066 are high performance, high speed, fet input amplifiers available in small packages: soic-8, msop, and sot-23-5. they are rated to work over the industrial tem- perature range of ?0 c to +85 c. frequency ?mhz 24 0.1 1000 gain ?db 9 110 100 21 18 15 12 6 3 0 ? ? g = +10 g = +5 g = +2 g = +1 v o = 200mv p-p figure 1. small signal frequency response soic-8 (r) 1 v out1 ?n1 + in1 ? s +v s v out2 ?n2 + in2 8 27 36 45 AD8066 (top view) sot-23-5 (rt) 1 2 3 top view (not to scale) 5 4 v out ad8065 ? s +in +v s ?n soic-8 (r) and msop (rm) 1 v out1 ?n1 + in1 ? s +v s v out2 ?n2 + in2 8 27 36 45 AD8066 (top view)
rev. b ? ad8065/AD8066?pecifications (@ t a = 25 c, v s = 5 v, r l = 1 k , unless otherwise noted.) parameter conditions min typ max unit dynamic performance ? db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 100 145 mhz g = +1, v o = 0.2 v p-p (AD8066) 100 120 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 42 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 7 mhz input overdrive recovery time g = +1, ?.5 v to +5.5 v 175 ns output recovery time g = ?, ?.5 v to +5.5 v 170 ns slew rate g = +2, v o = 4 v step 130 180 v/ m s settling time to 0.1% g = +2, v o = 2 v step 55 ns g = +2, v o = 8 v step 205 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p ?8 dbc f c = 5 mhz, g = +2, v o = 2 v p-p ?7 dbc fc = 1 mhz, g = +2, v o = 8 v p-p 73 dbc third order intercept f c = 10 mhz, r l = 100 w 24 dbm input voltage noise f = 10 khz 7 nv/ hz input current noise f = 10 khz 0.6 fa/ hz differential gain error ntsc, g = +2, r l = 150 w 0.02 % differential phase error ntsc, g = +2, r l = 150 w 0.02 degree dc performance input offset voltage v cm = 0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 m v/ o c input bias current soic package 2 6 pa t min to t max 25 pa input offset current 110pa t min to t max 1pa open-loop gain v o = 3 v, r l = 1 k w 100 113 db input characteristics common-mode input impedance 1000 2.1 g w pf differential input impedance 1000 4.5 g w pf input common-mode voltage range fet input range 5 to +1.7 ?.0 to +2.4 v usable range see theory of operation section ?.0 to +5.0 v common-mode rejection ratio v cm = ? v to +1 v ?5 ?00 db v cm = ? v to +1 v (sot-23) ?2 ?1 db output characteristics output voltage swing r l = 1 k w ?.88 to +4.90 4.94 to +4.95 v r l = 150 w 4.8 to +4.7 v output current v o = 9 v p? , sfdr ?0 dbc, f = 500 khz 35 ma short circuit current 90 ma capacitive load drive 30% overshoot g = +1 20 pf power supply operating range 5 24 v quiescent current per amplifier 6.4 7.2 ma power supply rejection ratio psrr 85 ?00 db
rev. b ad8065/AD8066 ? specifications parameter conditions min typ max unit dynamic performance ? db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 100 145 mhz g = +1, v o = 0.2 v p-p (AD8066) 100 115 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 40 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 7 mhz input overdrive recovery g = +1, ?2.5 v to +12.5 v 175 ns output overdrive recovery g = ?, ?2.5 v to +12.5 v 170 ns slew rate g = +2, v o = 4 v step 130 180 v/ m s settling time to 0.1% g = +2, v o = 2 v step 55 ns g = +2, v o = 10 v step 250 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p ?00 dbc f c = 5 mhz, g = +2, v o = 2 v p-p ?7 dbc fc = 1 mhz, g = +2, v o = 10 v p-p ?5 dbc third order intercept f c = 10 mhz, r l = 100 w 24 dbm input voltage noise f = 10 khz 7 nv/ hz input current noise f = 10 khz 1 fa/ hz differential gain error ntsc, g = +2, r l = 150 w 0.04 % differential phase error ntsc, g = +2, r l = 150 w 0.03 degree dc performance input offset voltage v cm = 0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 m v/ o c input bias current soic package 3 7 pa t min to t max 25 pa input offset current 210pa t min to t max 2pa open-loop gain v o = 10 v, r l = 1 k w 103 114 db input characteristics common-mode input impedance 1000 2.1 g w pf differential input impedance 1000 4.5 g w pf input common-mode voltage range fet input range 12 to +8.5 ?2.0 to +9.5 v usable range see theory of operation section ?2.0 to +12.0 v common-mode rejection ratio v cm = ? v to +1 v 85 ?00 db v cm = ? v to +1 v (sot-23) 82 ?1 db output characteristics output voltage swing r l = 1 k w 11.8 to +11.8 11.9 to +11.9 v r l = 350 w 11.25 to +11.5 v output current v o = 22 v p?, sfdr 60 dbc, f = 500 khz 30 ma short circuit current 120 ma capacitive load drive 30% overshoot g = +1 25 pf power supply operating range 5 24 v quiescent current per amplifier 6.6 7.4 ma power supply rejection ratio psrr 84 ?3 db (@t a = 25 c, v s = 12 v, r l = 1 k , unless otherwise noted.)
rev. b ? ad8065/AD8066 ?pecifications (@ t a = 25 c, v s = 5 v, r l = 1 k to 1.5 v, unless otherwise noted.) parameter conditions min typ max unit dynamic performance ? db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 125 155 mhz g = +1, v o = 0.2 v p-p (AD8066) 110 130 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 43 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 6 mhz input overdrive recovery time g = +1, ?.5 v to +5.5 v 175 ns output recovery time g = ?, ?.5 v to +5.5 v 170 ns slew rate g = +2, v o = 2 v step 105 160 v/ m s settling time to 0.1% g = +2, v o = 2 v step 60 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p 65 dbc f c = 5 mhz, g = +2, v o = 2 v p-p 50 dbc third order intercept f c = 10 mhz, r l = 100 w 22 dbm input voltage noise f = 10 khz 7 nv/ hz input current noise f = 10 khz 0.6 fa/ hz differential gain error ntsc, g = +2, r l = 150 w 0.13 % differential phase error ntsc, g = +2, r l = 150 w 0.16 degree dc performance input offset voltage v cm = 1.0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 m v/ o c input bias current soic package 1 5 pa t min to t max 25 pa input offset current 15pa t min to t max 1pa open-loop gain v o = 1 v to 4 v (ad8065) 100 113 db v o = 1 v to 4 v (AD8066) 90 103 db input characteristics common-mode input impedance 1000 2.1 g w pf differential input impedance 1000 4.5 g w pf input common-mode voltage range fet input range 0 to 1.7 0 to 2.4 v usable range see theory of operation section 0 to 5.0 v common-mode rejection ratio v cm = 1 v to 4 v 74 100 db v cm = 1 v to 2 v (sot-23) 78 91 db output characteristics output voltage swing r l = 1 k w 0.1 to 4.85 0.03 to 4.95 v r l = 150 w 0.07 to 4.83 v output current v o = 4 v p-p, sfdr 60 dbc, f = 500 khz 35 ma short circuit current 75 ma capacitive load drive 30% overshoot g = +1 5 pf power supply operating range 5 24 v quiescent current per amplifier 5.8 6.4 7.0 ma power supply rejection ratio psrr 78 100 db absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 v power dissipation . . . . . . . . . . . . . . . . . . . . . . . see figure 2 common-mode input voltage . . v ee ?0.5 v to v cc + 0.5 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.8 v storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +125 c operating temperature range . . . . . . . . . . . ?0 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the ad8065/AD8066 packages is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die will locally reach the junction temperature. at approximately 150 c, which is the glass transition temperature, the plastic will change its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8065/AD8066. exceeding a junction temperature of 175 c for an extended period of time can result in changes in the silicon devices, potentially causing failure.
rev. b ad8065/AD8066 ? ambient temperature ? c 2.0 1.5 0 ?0 100 ?0 maximum power dissipation ?w ?0 0 20 4 06080 1.0 0.5 soic-8 sot-23-5 msop-8 figure 2. maximum power dissipation vs. temperature for a four-layer board the still-air thermal properties of the package and pcb ( j a ), ambient temperature ( t a ), and the total power dissipated in the package ( p d ) determine the junction temperature of the die. the junction temperature can be calculated as follows tt p ad j =+ () q j a the power dissipated in the package ( p d ) is the sum of the quies- cent pow er dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins ( v s ) times the quiescent current ( i s ). assuming the load ( r l ) is referenced to midsupply, then the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load ( v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p quiescent power total drive power load power d =+ () pvi vv r v r dss s out l out l = () + ? ? ? - 2 2 rms output voltages should be considered. if r l is referenced to v s , as in single-supply operation, then the total drive power is v s i out . if the rms signal levels are indeterminate, then consider the worst case, when v out = v s /4 for r l to midsupply pvi v r dss s l = () + (/) 4 2 in single-supply operation with r l referenced to v s , worst case is v out = v s /2. airflow will increase heat dissipation effectively reducing j a . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes, will reduce the j a . care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the board layout section. figure 2 shows the maximum safe power dissipation in the package versus the ambient temperature for the soic-8 (125 c/w) and sot-23-5 (180 c/w) packages on a jedec standard four- layer board. j a values are approximations. output short circuit shorting the output to ground or drawing excessive current for the ad8065/AD8066 will likely cause catastrophic failure. ordering guide model temperature range package description package outline branding information ad8065ar ad8065ar-reel ad8065ar-reel7 ad8065art-reel ad8065art-reel7 AD8066ar AD8066ar-reel7 AD8066ar-reel AD8066arm-reel AD8066arm-reel7 ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? ?0? to +85? 8-lead soic 8-lead soic 8-lead soic 5-lead soic sot-23 5-lead soic sot-23 8-lead soic 8-lead soic 8-lead soic 8-lead soic msop-8 8-lead soic msop-8 r-8 r-8 r-8 rt-5 hra rt-5 hra r-8 r-8 r-8 rm-8 h1b rm-8 h1b caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8065/AD8066 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. b ? ad8065/AD8066?ypical performance characteristics frequency ?mhz 24 0.1 1000 gain ?db 9 110 100 21 18 15 12 6 3 0 ? ? g = +10 g = +5 g = +2 g = +1 v o = 200mv p-p tpc 1. small signal frequency response for various gains frequency ?mhz 6 0.1 1000 gain ?db 0 110 100 4 2 ? ? ? v s = 5v g = +1 v o = 200mv p-p v s = 5v v s = 12v tpc 2. small signal frequency response for various supplies (see test circuit 1) frequency ?mhz 2 0.1 1000 gain ?db ? 110 100 1 0 ? ? ? g = +1 v s = 5v v s = 12v ? v o = 2v p-p tpc 3. large signal frequency response for various supplies (see test circuit 1) frequency ?mhz 6.9 0.1 gain ?db 6.5 110 100 6.4 6.3 6.2 g = +2 v out = 0.2v p-p 6.0 r l = 150 v out = 0.7v p-p v out = 1.4v p-p 6.8 6.7 6.6 6.1 5.9 tpc 4. 0.1 db flatness frequency response (see test circuit 2) frequency ?mhz 9 0.1 1000 gain ?db 6 110 100 8 7 5 4 3 v s = 5v g = +2 v o = 200mv p-p v s = 5v v s = 12v tpc 5. small signal frequency response for various supplies (see test circuit 2) frequency ?mhz 0.1 1000 gain ?db 6 110 100 8 7 5 4 3 v s = 5v g = +2 v s = 5v v s = 12v 2 1 0 tpc 6. large signal frequency response for various supplies (see test circuit 2) (default conditions 5 v, c l = 5 pf, r l = 1 k , v out = 2 v p-p, temperature = 25 c)
rev. b ad8065/AD8066 ? frequency ?mhz 9 6 ? 0.1 1000 110 100 3 ? ? 0 v o = 200mv p-p g = +1 c l = 5pf c l = 25pf rsnub = 20 c l = 25pf c l = 20pf gain ?db tpc 7. small signal frequency response for various c load (see test circuit 1) frequency ?mhz 8 6 ? 0.1 1000 1 gain ?db 10 100 4 2 ? 0 ? ? v out = 2v p-p v out = 4v p-p v out = 0.2v p-p g = +2 tpc 8. frequency response for various output amplitude (see test circuit 2) frequency ?mhz 14 12 ? 0.1 1000 1 gain ?db 10 100 10 8 ? 6 4 2 0 v o = 200mv p-p g = +2 r f = r g = 500 , r s = 250 r f = r g = 1k , r s = 500 , c f = 3.3pf r f = r g = 1k , r s = 500 r f = r g = 500 , r s = 250 , c f = 2.2pf tpc 9. small signal frequency response for various r f /c f (see test circuit 2) frequency ?mhz 8 6 ? 0.1 1000 1 gain ?db 10 100 4 2 ? 0 ? ? g = +2 v o = 200mv p-p c l = 25pf c l = 55pf c l = 5pf tpc 10. small signal frequency response for various c load (see test circuit 2) frequency ?mhz 8 7 0 1000 1 gain ?db 10 100 6 5 1 4 3 2 0 g = +2 v o = 200mv p-p r l = 100 r l = 1k tpc 11. small signal frequency response for various r load (see test circuit 2) fre quency ?mhz 80 60 ?0 0.01 0.1 o pen-loop gain ?db 110 100 40 20 0 120 60 ?80 0 ?0 ?20 p hase ?degrees 1k gain phase tpc 12. open-loop response
rev. b ? ad8065/AD8066 frequency ?mhz 0.1 100 110 ?0 ?0 ?20 distortion ?dbc ?0 ?0 ?00 ?0 ?0 ?0 ?10 g = +2 hd3 r load = 150 hd3 r load = 1k hd2 r load = 150 hd2 r load = 1k tpc 13. harmonic distortion vs. frequency for various loads (see test circuit 2) g = +2 hd3 r load = 150 hd2 r load = 150 hd2 r load = 300 v s = 12v f = 1mhz hd3 r load = 300 output amplitude ?v p-p 013 123456789101112 ?0 ?0 distortion ?dbc ?0 ?00 ?10 ?20 ?0 ?0 ?0 14 15 ?0 tpc 14. harmonic distortion vs. amplitude for various loads v s = 12 v (see test circuit 2) fre quency ?mhz in tercept point ?dbm 50 20 1 10 v s = 5v v s = +5v 40 15 45 35 30 25 r l = 100 v s = 12v tpc 15. third order intercept vs. frequency and supply voltage frequency ?mhz 0.1 100 110 ?0 distortion ?dbc ?0 ?0 ?00 ?0 ?0 ?0 ?10 hd3 g = +2 hd3 g = +1 hd2 g = +2 hd2 g = +1 tpc 16. harmonic distortion vs. frequency for various gains (see test circuits 1 and 2) frequency ?mhz ?0 ?0 ?20 0.1 10 1 distortion ?dbc ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 g = +2 v s = 12v hd2 v o = 20v p-p hd3 v o = 2v p-p hd2 v o = 2v p-p hd3 v o = 20v p-p hd2 v o = 10v p-p hd3 v o = 10v p-p tpc 17. harmonic distortion vs. frequency for various amplitudes (see test circuit 2) frequency ?hz 100 1 10 10m 10 100 1k 10k 100k 1m 100m 1g noise ?nv/ hz tpc 18. voltage noise
rev. b ad8065/AD8066 ? g = +1 50mv/div 20ns/div tpc 19. small signal transient response 5 v supply (see test circuit 11) g = +1 2v/div 80ns/div v s = 12v v out = 2v p-p v out = 4v p-p v out = 10v p-p tpc 20. large signal transient response (see test circuit 1) g = 1 1.5v/div 100ns/div in out tpc 21. output overdrive recovery (see test circuit 3), v s = 5 v g = +1 50mv/div 20ns/div c l = 20pf c l = 5pf tpc 22. small signal transient response 5 v ( see test circuit 1) 5s g = +2 2v/div 80ns/div v s = 12v v out = 10v p-p v out = 2v p-p tpc 23. large signal transient response (see test circuit 2) g = +1 1.5v/div 100ns/div in out tpc 24. input overdrive recovery (see test circuit 1), v s = 5 v
rev. b ?0 ad8065/AD8066 t = 0 64 s/div 2mv/div +0.1% ?.1% v in = 140mv/div v out ?2v in tpc 25. long-term settling time (see test circuit 8) temperature ? c 0 ?0 25 85 35 input bias current ?pa 45 55 65 75 ? ?0 ?5 ?0 ?5 ? b +i b tpc 26. input bias current vs. temperature common-mode voltage ?v 0.3 0 ?.3 ?4 12 ?2 offset voltage ?mv ?0 ? ? ? ? 0 2 4 6 8 10 0.2 0.1 ?.1 ?.2 14 v s = +5v v s = 12v v s = 5v tpc 27. input offset voltage vs. common-mode voltage 0.1% 2mv/div 10ns/div 0.1% t = 0 v out ?2v in v in = 500mv/div tpc 28. 0.1% short-term settling time (see test circuit 8) 0 i b ? a 36 30 24 18 12 6 ? ?5 ?5 ?0 0 i b ?pa ?2 8 ? ?0 0 ? 2 ? 4 ? 6 common-mode voltage ?v 10 12 42 ? b +i b ? b +i b fet input stage bjt input stage ?0 ?0 5 tpc 29. input bias current vs. common-mode voltage range * input offset voltage ?mv 35 15 0 ?.0 2.0 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 30 20 10 5 40 25 n = 299 sd = 0.388 mean = ?.069 tpc 30. input offset voltage * see input and output overload behavior section.
rev. b ad8065/AD8066 ?1 frequency ?mhz 0.1 100 110 ?0 cmrr ?db ?0 ?0 ?0 ?0 ?0 ?0 ?00 v s = 5v v s = 12v tpc 31. cmrr vs. frequency (see test circuit 5) i load ?ma 0.30 0.25 0 040 10 output saturation voltage ?v 20 30 0.20 0.15 0.10 0.05 v ol ?v ee v cc ?v oh tpc 32. output saturation voltage vs. output load current frequency ?mhz 0 ?0 ?0 0.01 1000 0.1 psrr ?db 110 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 + psrr ?psrr ?00 tpc 33. psrr vs. frequency (see test circuits 7 and 9) frequency ?hz 1k 100m 10k output impedance ? 100k 1m 10m g = +1 g = +2 0.01 100 100 10 1 0 0.1 tpc 34. output impedance vs. frequency (see test circuits 4 and 6) temperature ? c 80 30 25 85 35 output saturation voltage ?mv 45 55 65 75 75 60 45 40 35 70 65 55 50 v ol ?v ee v cc ?v oh tpc 35. output saturation voltage vs. temperature frequency ?mhz 0.1 1 crosstalk ?db 10 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 b to a a to b v in = 2v p-p g = +1 tpc 36. crosstalk vs. frequency (see test circuit 10)
rev. b ?2 ad8065/AD8066 temperature ? c 6.60 6.25 ?0 80 ?0 supply current ?ma 0204 060 6.55 6.50 6.45 6.35 6.30 6.40 v s = +5v v s = 12v v s = 5v tpc 37. quiescent supply current vs. temperature for various supply voltages i load ?ma 125 120 80 040 10 open-loop gain ?db 20 30 105 95 90 85 115 110 100 v s = 5v v s = +5v v s = 12v tpc 38. open-loop gain vs. load current for various supply voltages ad8065 +v cc v in ? ee 4.7 f 0.1 f 24.9 rsnub 0.1 f 4.7 f c load fet probe 49.9 1k test circuit 1. g = +1 ad8065 +v cc v in ? ee 4.7 f 0.1 f 2.2pf rsnub 0.1 f 4.7 f 49.9 499 499 249 c load fet probe 1k test circuit 2. g = +2 t est ciruits soic pinout
rev. b ad8065/AD8066 ?3 v in 49.9 ad8065 +v cc ? ee 4.7 f 0.1 f 2.2pf 0.1 f 4.7 f 499 499 249 fet probe 1k test circuit 3. g = ? ad8065 +v cc ? ee 4.7 f 0.1 f 24.9 0.1 f 4.7 f network analyzer s22 test circuit 4. output impedance g = +1 v in 49.9 ad8065 +v cc ? ee 4.7 f 0.1 f 0.1 f 4.7 f 499 499 fet probe 1k 499 499 test circuit 5. cmrr ad8065 +v cc ? ee 0.1 f 4.7 f 499 499 249 network analyzer s22 4.7 f 0.1 f test circuit 6. output impedance g = +2
rev. b ?4 ad8065/AD8066 ad8065 ? ee 24.9 0.1 f 4.7 f +v cc fet probe 1k v in 1v p-p 49.9 test circuit 7. positive psrr test circuit 8. settling time test circuit 9. negative psrr test circuit 10. crosstalk ?AD8066 ad8065 +v cc v in ? ee 4.7 f 0.1 f 2.2pf 976 0.1 f 4.7 f 499 499 249 to scope 49.9 49.9 ad8065 +v cc ? ee 4.7 f 0.1 f fet probe 49.9 24.9 v in 1v p-p 1k 24.9 49.9 24.9 1k 0.1 f 4.7 f v in +5v ?v 1k drive side receive side 0.1 f 4.7 f fet probe
rev. b ad8065/AD8066 ?5 249 0.1 f v in 1.5v 1.5v 1.5v 4.7 f 499 499 5v 49.9 2.2pf 1k fet probe test circuit 11. single supply
rev. b ?6 ad8065/AD8066 noninverting closed-loop frequency response solving for the transfer function v v frr rrs f r o i crossover g f fg crossover g = + ++ 2 2 p p () () where f crossover is the frequency where the amplifier? open-loop gain equals 0 db. at dc v v rr r o i fg g = + closed-loop ? db frequency ff r rr db crossover g fg - = + 3 inverting closed-loop frequency response v v fr sr r f r o i crossover f fg crossover g = - ++ 2 2 p p () at dc v v r r o i f g =- closed-loop ? db frequency ff r rr db crossover g fg - = + 3 theory of operation the ad8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed jfet input stage with analog devices?extra fast complementary bipolar process, resulting in an outstanding combination of precision and speed. supply voltage range is from 5 v to 24 v. the amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 v of either power supply while sourcing or sinking up to 30 ma. also featured is a single-supply input stage that handles common- mode signals from below the negative supply to within 3 v of the positive rail. operation beyond the jfet input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. the amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. with voltage noise of 7 nv/ hz and ?8 dbc distortion for 1 mhz 2 v p-p signals, the ad8065/AD8066 are a great choice for high resolution data acquisition systems. its low noise, sub-pa input current, precision offset, and high speed make it a superb preamp for fast photodiode applications. the speed and output drive capability of the ad8065/AD8066 also make them useful in video applications. closed-loop frequency response the ad8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in figure 3. basic closed-loop frequency response for inverting and noninverting configurations can be derived from the shown schematics. r f a v o r g v i v e frequency ?mhz 80 60 0.01 100 open-loop gain (a) ?db 0.1 1 10 40 20 0 f crossover = 65mhz a = (2 p f crossover )/s r f v e a v o r g v i figure 3. open-loop gain vs. frequency and basic connections
rev. b ad8065/AD8066 ?7 actual distortion performance depends on a number of variables: the closed-loop gain of the application whether it is inverting or noninverting amplifier loading signal frequency and amplitude board layout also see tpcs 13 to 17. the lowest distortion will be obtained with the ad8065 used in low gain inverting applications, since this eliminates common-mode effects. higher closed-loop gains result in worse distortion performance. input protection the inputs of the ad8065/AD8066 are protected with back-to- back diodes between the input terminals as well as esd diodes to either power supply. this results in an input stage with picoamps of input current that can withstand up to 1500 v esd events (human body model) with no degradation. excessive power dissipation through the protection devices will destroy or degrade the performance of the amplifier. differential voltages greater than 0.7 v will result in an input current of approximately (| v + ? v |?0.7 v )/ r i , where r i is the resistance in series with the inputs. for input voltages beyond the positive supply, the input current will be approximately ( v i ? v cc ?0.7)/ r i . beyond the negative supply, the input current will be about ( v i ? v ee + 0.7)/ r i . if the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 v or to input voltages beyond the amplifier power supply, input current should be limited to 30 ma by an appropriately sized input resistor ( r i ) as shown in figure 5. r i v i v o ad8065 r i > (| v + ?v | ?0.7v) 30ma fo r large | v + ?v | r i > (v i ?v ee ?0.7v) 30ma r i > (v i ?v ee + 0.7v) 30ma for v i beyond supply voltages figure 5. current limiting resistor thermal considerations with 24 v power supplies and 6.5 ma quiescent current, the ad8065 dissipates 156 mw with no load. the ad8065/AD8066 dissipate 312 mw. this can lead to noticeable thermal effects, especially in the small sot-23-5 (thermal resistance of 160 c w). v os temperature drift is trimmed to guarantee a max drift of 17 m v c, so it can change up to 0.425 mv due to warm-up effects for an ad8065/AD8066 in a sot-23-5 package on 24 v. i b increases by a factor of 1.7 for every 10 c rise in temperature. i b will be close to 5 times higher at 24 v supplies as opposed to a single 5 v supply. heavy loads will increase power dissipation and raise the chip junction temperature as described in the maximum power d issipation section. care should be taken to not exceed the rated power dissipation of the package. the closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, ( r f + r g )/ r g . this simple model is accurate for noise gains above 2. the actual bandwidth of circuits with noise gains at or below 2 will be higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. v o r f a r g v i i b r s i b + +v os figure 4. voltage feedback amplifier dc errors figure 4 shows a voltage feedback amplifier? dc errors. for both inverting and noninverting configurations v (error) i r rr r irv rr r ob+s gf g b- f os gf g = + ? ? ? - + + ? ? ? the voltage error due to i b + and i b is minimized if r s = r f r g (though with the ad8065 input currents at less than 20 pa overtemperature, this is likely not a concern). to include common-mode and power supply rejection effects, total v os can be modeled as vv v psr v cmr os os nom scm =++ dd v os nom is the offset voltage specified at nominal conditions. d v s is the change in power supply from nominal conditions. psr is the power supply rejection. v cm is the change in common-mode voltage from nominal conditions. cmr is the common-mode rejection. wideband operation test circuits 1, 2, and 3 show the circuits used for wideband characterization for gains of +1, +2, and ?. source impedance at the summing junction (r f r g ) will form a pole in the amplifier? loop response with the amplifier? input capacitance of 6.6 pf. this can cause peaking and ringing if the time constant formed is too low. feedback resistances of 300 w to 1 k w are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. peaking in the frequency response can be compensated with a small capacitor (c f ) in parallel with the feedback resistor, as illustrated in tpc 9. this shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting g = +2 amplifier. for the best settling times and the best distortion, the impedances at the ad8065/ad 8066 input terminals should be matched. this minim izes nonlinear common-mode capacitive effects that can degrade ac performance.
rev. b ?8 ad8065/AD8066 layout, grounding, and bypassing considerations power supply bypassing power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. the purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. decoupling schemes are designed to minimize the bypassing imped- ance at all frequencies with a parallel combination of capacitors. 0.1 m f (x7r or npo) chip capacitors are critical and should be as close as possible to the amplifier package. the 4.7 m f tantalum capacitor is less critical for high frequency bypassing, and in most cases, only one per board is needed at the supply inputs. grounding a ground plane layer is important in densely packed pc boards to spread the current minimizing parasitic inductances. however, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. the length of the current path is directly proportional to the magnitude of parasitic inductances and therefore the high frequency imped- ance of the path. high speed currents in an inductive ground return will create an unwanted voltage noise. input and output overload behavior the ad8065/ad 8066 have internal circuitry to guard against phase rever sal due to overdriving the input stage. a simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in figure 6. the circuit is arranged such that when the input common-mode voltage exceeds a certain threshold, the input jfet pair? bias current will turn off, and the bias current of an auxiliary npn pair will turn on, taking over control of the amplifier. when the input common-mode voltage returns to a viable operating value, the fet stage turns back on, the npn stage turns off, and normal operation resumes. the npn pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. for operation beyond the fet stage? common-mode limit, the amplifier? v os will change to the npn pair? offset (mean of 160 m v, standard deviation of 820 m v), and i b will increase to the npn pair? base current up to 45 m a (see tpc 29). switchback, or recovery time, is about 100 ns, as shown in tpc 24. the output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. this helps output recovery time. output recovery from a 0.5 v output overdrive on a 5 v supply is shown in tpc 21. vthreshold vbias s v p to rest of amp v ee v cc s v n figure 6. simplified input stage
rev. b ad8065/AD8066 ?9 the length of the high frequency bypass capacitor leads is most critical. a parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. place the ground leads of the bypass capacitors at the same physical location. because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. for the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. leakage currents poor pc board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the ad8065/AD8066. any voltage differential between the inputs and nearby runs will set up leak age currents through the pc board insulator, for example, 1v /100 g w = 10 pa. similarly any contaminants on the board can create significant leakage (skin oils are a common problem). to significantly reduce leakages, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. this way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. for the guard ring to be completely effective it must be driven by a relatively low impedance source and should com- pletely surround the input leads on all sides, above and below using a multilayer board. another effect that can cause leakage currents is the charge absorption of the insulator material itself. minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. also, low absorption materials, such as teflon or ceramic, may be necessary in some instances. input capacitance along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. a few pf of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier? gain, causing peak ing of the frequency response or even oscillations, if severe enough. it is recommended that the external passive compo nents that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. the ground and power planes must be kept at a small distance away from the input pins on all layers of the board. output capacitance to a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. there are two methods to effectively minimize their effect. 1) as shown in figure 7, put a small value resistor (r s ) in series with the output to isolate the load capacitor from the amp? output stage. a good value to choose is 20 w (see tpc 7). r s = 20 v i ad8065 c l v o figure 7. output isolation resistor 2) increase the phase margin with higher noise gains or adding a pole with a parallel resistor and capacitor from ?n to the output.
rev. b ?0 ad8065/AD8066 input-to-output coupling the output signal traces should not be parallel with inputs in order to minimize capacitive coupling between the inputs and output. wideband photodiode preamp figure 8 shows an i/v converter with an electrical model of a photodiode. the basic transfer function is v ir sc r out photo f ff = + 1 where i photo is the output current of the photodiode, and the parallel combination of r f and c f set the signal bandwidth. the stable bandwidth attainable with this preamp is a function of r f , the gain bandwidth product of the amplifier, and the total capacitance at the amplifier? summing junction, including c s and the amplifier input capacitance. r f and the total capacitance produce a pole in the amplifier? loop transmission that can result in peaking and instability. adding c f creates a zero in the loop transmission that compensates for the pole? effect and reduces the signal bandwidth. it can be shown that the signal bandwidth resulting in a 45 phase margin ( f (45) ) is defined by the expression f f rc cr fs () 45 2 = p where: f cr is the the amplifier crossover frequency. r f is the the feedback resistor. c s is the the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). the value of c f that produces f (45) can be shown to be c c rf f s fcr = 2 p the frequency response in this case will show about 2 db of peaking and 15% overshoot. doubling c f and cutting the band- width in half will result in a flat frequency response, with about 5% transient overshoot. the preamp? output noise over frequency is shown in figure 9. frequency ?hz voltage noise ?nv/ hz 2 r f c f 2 r f (c f + c s + c m + 2c d ) (c s + c m + 2c d + c f ) /c f rf noise ven (c f + c s + c m + 2c d )/c f f 3 f 2 f 3 = ven f 1 f 2 = f 1 = 1 1 f cr noise due to amplifier figure 9. photodiode voltage noise contributions the pole in the loop transmission translates to a zero in the ampli- fier? noise gain, leading to an amplification of the input voltage noise over frequency. the loop transmission zero introduced by c f limits the amplification. the noise gain? bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. keeping the input terminal impedances matched is recommended to eliminate common- mode noise peaking effects, which will add to the output noise. v o r f c f c m r f c m c d c f + c s r sh = 10 11 c s v b iphoto figure 8. wideband photodiode preamp
rev. b ad8065/AD8066 ?1 table i. rms noise contributions of photodiode preamp rms noise with r f = 50 k w , contributor expression c s = 15 pf, c f = 2 pf rf ( 2) 24 157 2 kt r f f . 64.5 m v amp to f 1 ven f 1 2.4 m v amp (f 2 ? 1 ) ven cc c c c ff sm f d f +++ () 2 21 31 m v amp (past f 2 ) ven cc c c c f sm d f f +++ () . 2 157 3 260 m v total 270 m v v cc v ee 1 / 2 AD8066 4.7 f 0.1 f r s1 4.7 f 0.1 f v n 2.2pf 500 r 2 v p 1 / 2 AD8066 4.7 f 0.1 f 4.7 f 0.1 f ad8065 4.7 f 0.1 f 4.7 f 0.1 f v o r g v cc v ee v cc v ee 500 r 4 r s2 500 r 1 500 r 3 r f = 500 2.2pf r f = 500 figure 10. high speed instrumentation amplifier integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. table i summarizes approximations for the amplifier and feedback and source resis- tances. noise components for an example preamp with r f = 50 k w , c s = 15 pf, and c f = 2 pf (bandwidth of about 1.6 mhz) are also listed.
rev. b ?2 ad8065/AD8066 high speed jfet input instrumentation amplifier figure 10 shows an example of a high speed instrumentation amplifier with high input impedance using the ad8065/AD8066. the dc transfer function is vvv r out n p g =- + ? ? ? () 1 1000 for g = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 w for 50 w source impedance). the bandwidth for g = +1 will be 50 mhz. for higher gains, the bandwidth will be set by the preamp, equaling inamp -3db = ()/() fr r cr g f 2 common-mode rejection of the inamp will be primarily deter- mined by the match of the resistor ratios r1:r2 to r3:r4. it can be estimated v v o cm = - + () () dd dd 12 112 the summing junction impedance for the preamps is equal to r f 0.5(r g ). this is the value to be used for matching purposes. video buffer the output current capability and speed of the ad8065 make it useful as a video buffer, shown in figure 11. the g = +2 configuration compensates for the voltage division of the signal due to the signal termination. this buffer maintains 0.1 db flatness for signals up to 7 mhz, from low amplitudes up to 2 v p-p (tpc 4). differential gain and phase have been measured to be 0.02% and 0.028 at 5v supplies. v s 4.7 f 0.1 f 2.2pf 499 249 75 499 v i ad8065 v s 4.7 f 0.1 f 75 v o figure 11. video buffer
rev. b ad8065/AD8066 ?3 outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa 5-lead plastic surface mount package [sot-23] (rt-5) dimensions shown in millimeters pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 1 3 4 5 2 0.22 0.08 0.60 0.45 0.30 10 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 compliant to jedec standards mo-178aa 2.90 bsc 8-lead microsoic package [msop] (rm-8) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc compliant to jedec standards mo-187aa coplanarity 0.10
?4 c02916??/03(b) printed in u.s.a. rev. b revision history location page 2/03?ata sheet changed from rev. a to rev. b. changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to test circuit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to test circuit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 changes to noninverting closed-loop frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 changes to inverting closed-loop frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 updated figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 changes to figures 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to high speed jfet instrumentation amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to video buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8/02?ata sheet changed from rev. 0 to rev. a. added AD8066 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal added soic-8 (r) and msop-8 (rm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 new figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to tpcs 18, 25, and 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 new tpc 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added test circuits 10 and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 msop (rm-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ad8065/AD8066

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